The present invention is related to semiconductor devices, and more particularly to semiconductor devices having local interconnects and contact plugs, such as logic devices, DRAMs, and SRAMs, and fabrication of the same.
Various contacts and interconnects are formed in the fabrication of semiconductor devices. For example, in fabrication of static random access memories SRAMs), local interconnects are used to increase packing density. SRAMs use local interconnections to connect its memory storage areas with its memory control areas and contact plugs to control its transistors. Dynamic random access memories (DRAMs) include memory cell arrays that store information and peripheral circuitry to control the memory cell array. The DRAM devices have cell contacts to peripheral circuitry. DRAMs may also use buried bit lines to contact the memory cell transistors in the DRAM arrays.
There are continuing goals in semiconductor fabrication to both reduce the number of masks or steps and to simplify steps needed to fabricate the contacts and interconnections for memory cells (e.g., contact plugs, local interconnects, and cell contacts in DRAMs, SRAMs and logic devices). Because the formation of interconnection in memory devices is complex and expensive, there is a need for methods that have fewer and simpler process steps to form the interconnections. Likewise, there is a continuing goal to shrink the memory cell size thereby maximizing density of the resulting chip.
For example, conventional (prior art) SRAM (or LSI logic device) fabrication processes require at least two mask steps to form the local interconnections and the contact plugs to the transistor gates (see prior art shown in FIGS. 1-4). Specifically, with reference to prior art FIG. 1, in such conventional processes, after formation of an array of transistors (typically field-effect transistors or FETs) 1, an insulating cap 2 is patterned (a first masking step for formation of the interconnections) and etched to expose a portion 3 of a transistor gate 4 for contact. An insulating layer 5 is deposited over the entire device and is planarized (prior art FIG. 2). Next, a second masking step must be performed. Namely, the insulating layer 5 must then be patterned and etched to form contact holes for the contact plugs 6 and a relatively wide trench 7 for the local interconnect (prior art FIG. 3). A self-aligned contact (SAC) etch or a pedestal etch must then be performed to ensure that the contact will not short to adjacent transistor gates.
The insulating layer 5 must be etched down to the transistor gate contact area 3 (see prior art FIGS. 2 and 3). Last, interconnect material is deposited to form the contact plugs 8 and local interconnect 9 (prior art FIG. 4). Since the conventional fabrication methods require that the etch stop when it reaches the insulating cap 2, the transistor contact plugs and the local interconnect cannot be formed at the same time. That is, to form the contact area 3 (prior art FIG. 3) of the local interconnect 9, there must be a first masking and etching step (as described above). A second mask and etch step is later performed to form the holes 6 for the contact plugs 8. Accordingly, two mask process steps are needed to form the contact plugs 8 and the local interconnect 9. (Thus, the contact plugs and contact for the local interconnect are not formed at the xe2x80x9csame timexe2x80x9d but require separate masking and etching steps.) Further, SAC etches or pedestal etches are required, making the process more complex.
Similar problems are encountered when fabricating cell contacts and buried bit lines in various semiconductor devices, such as DRAMs. Specifically, prior art methods typically follow the cell-over-bit line processes well known to those skilled in the art. Such prior art processes all require two separate masking steps to form cell contacts and the buried bit lines. Extra mask steps add significant cost and complexity to the fabrication process. Further, the prior art methods require that the contacts be defined between or through buried bit lines (see prior art FIG. 5). Accordingly, contact between the lower cell plate to the contact plug is difficult to define.
Provided herein are methods for the fabrication of electrical interconnects in semiconductor devices. In one embodiment of the invention, a substrate is provided. The substrate includes two or more transistors with active areas therebetween, the transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are completely covered by an insulating cap). An insulating layer overlying the transistors and the active areas is then deposited, where upon a hard mask is created and patterned to form a contact plug/interconnect opening over a first active area and a portion of a first transistor immediately adjacent the first active area. A spacer is then formed within the contact plug/interconnect opening thereby forming two contact holes. Insulating material overlying one or more of the active areas is removed including material over the first active area such that the active areas are exposed. A portion of the gate region of the first transistor is then exposed and interconnect material is deposited within the contact plug/interconnect opening onto the exposed portion of the gate region of the first transistor and the first active area. Accordingly, the exposed portion of the gate region of the first transistor is electrically connected to the first active area (i.e., a contact plug/interconnect is formed).
Another embodiment of the present invention methods pertains to formation of electrical interconnects and buried bit lines in a semiconductor device. The method generally comprises providing a substrate having two or more transistors with active areas therebetween. An insulating layer overlying the transistors and active areas is next formed and a hard mask is deposited over the insulating layer. The hard mask is patterned to define cell contacts above the active areas and buried bit lines between the cell contacts. A portion of the insulating layer is preferably removed to form cell contact trenches and buried bit line trenches. Spacers may then be created to substantially fill the buried bit line trenches. Portions of the insulating layer within the cell contact trenches are next removed to expose the active areas as the cell contacts. The spacers are then partially or substantially recessed within the buried bit line trenches, conductive material is deposited over the recessed spacers to substantially fill the buried bit line trenches and within the cell contact trenches to form the same.
Several embodiments of semiconductor devices having such electrical interconnects made by the methods disclosed herein are also disclosed.
All of the specifically described methods and semiconductor devices are set forth for illustration of the methods and devices of the present invention. It is understood, however, that the present invention is not limited to those specifically described embodiments of the methods and devices.